The invention relates to computer system memory architectures and, more particularly, to the control of memory access operations based on a characteristic of the entity requesting the memory access.
Many current computer system memory architectures use synchronous random access memories (synchronous RAM) such as synchronous dynamic random access memory (SDRAM), SyncLink dynamic random access memory (SLDRAM), and Rambus dynamic random access memory (RDRAM) memory. The SyncLink standard has been assigned the tentative designation of IEEE-1596.7 by the Microprocessor & Microcomputer Standards Committee (MMSC) of the Institute of Electrical and Electronics Engineers (IEEE). The Rambus.RTM. standard is published by Rambus, Incorporated of Mountain View, Calif.
In addition to providing inherently faster operation than previous types memories, synchronous RAM may generally be organized into banks. Banks represent a physical compartmentalization of memory space, where each bank may correspond to a unit or array of physical memory. A bank may be further divided into pages, where a page is typically defined in terms of a row address. That is, all those memory locations in a bank having a common row address are said to be on the same page of memory.
One feature of banked memory systems is that consecutive memory access operations to a common page may be performed faster than consecutive memory access operations directed to different pages within the same bank. As shown in FIG. 1, the time to perform first access 100 (directed to a first page in a first bank) includes the time needed to select the target page 102 and the time to select the uniquely targeted memory location 104. If second access 106 is directed to a memory location in the same page, the only time required to complete the memory transfer is that needed to select the target location 108; no time is required for page selection. If a subsequent, third access 110 is directed to a different page in the same bank however, the previously selected (open) page must be closed (an operation referred to as precharging 112) before access 110 may proceed. Following precharge operation 112, access 110 continues through page selection 114 and data selection 116 phases. Because precharge operations require some time to complete, they generally limit the speed with which a sequence of memory access operations may be performed. (Use of multiple banks may allow the time for some memory precharge operations to be hidden. For example, if a first memory access is to a first bank, and a second memory access is to a second bank, the precharge operation for the first bank may occur while initiating memory access to the second bank.)
Some attempts have been made, based on the ability to keep one or more pages open simultaneously (generally limited to one page per bank), to minimize data transfer interruptions caused by precharge time intervals. As indicated above, by leaving a page open after completing a memory access operation the precharge time penalty is avoided when a subsequent bank access is directed to that same page (a page hit). Conversely, when a subsequent bank access is to a different page (a page miss), the open page must be closed and the precharge operation performed before the memory access operation may proceed. Therefore, while there exists benefits to leaving a page open in the event there are frequent page hits, there also exists significant time penalties associated with a large number of page misses when pages are kept/left open.
Thus, there is a need for a technique that maintains a recently accessed memory page in the open state if subsequent access operations are likely to generate page hits, and closes the page if subsequent access operations are likely to generate page misses.